Semiconductor devices and other types of microelectronic devices have a die attached to a ceramic chip carrier, organic printed circuit board, lead frame, or other type of interposing structure. The microelectronic dies can be attached to interposing structures using Direct Chip Attach (DCA), flip-chip bonding, or wire-bonding to electrically connect the integrated circuitry in the dies to the wiring of the interposing structures. In typical DCA or flip-chip methods, very small bumps or balls of a conductive material (e.g., solder) are deposited onto the contacts of a die. The bumps are then connected to corresponding terminals on an interposing structure.
Copper is widely used for the wiring in semiconductor devices. For example, the wiring in the integrated circuitry of many high performance devices is composed of copper. The bond-pads of many microelectronic dies are also made from copper. One problem of copper bond-pads, however, is that copper easily oxidizes and corrodes in the presence of oxygen and water. As a result, copper bond-pads must be protected to prevent oxidation and/or corrosion that could possibly impair or destroy the device.
FIG. 1 is a cross-sectional view illustrating a portion of a microelectronic die 10 having substrate 11 with a copper bond-pad 20. The die 10 in FIG. 1 further includes passivation layers including a first dielectric layer 32 (e.g., silicon dioxide), a second dielectric layer 34 (e.g., silicon nitride), and a third dielectric layer 36 (e.g., polyimide). The die 10 further includes a cap 40 having a barrier layer 42 and a metal layer 44 over the barrier layer 42. The cap 40 is formed by constructing a first mask over the first and second dielectric layers 32 and 34, and etching holes through the first and second dielectric layers 32 and 34 over the bond-pad 20. The barrier layer 42 and the metal layer 44 are then deposited onto the workpiece 10. The process of forming the cap 40 further includes constructing a second mask on top of the metal layer 44 from a resist 50, developing the resist 50 to expose the areas of the metal layer 44 over the upper portions of the third dielectric layer 36, and then etching the metal layer 44 and the barrier layer 42 down to the third dielectric layer 36 using a reactive ion etch. The resist 50 is subsequently stripped from the workpiece 10 to leave the cap 40 over the copper bond-pad 20.
One problem with the copper interconnect structure illustrated in FIG. 1 is that it is relatively expensive to manufacture because this process requires a first mask to form the openings over the bond-pad 20 and a second mask to form the pattern of resist 50 over the metal layer 44. Masks are expensive to construct because they require very expensive photolithography equipment to achieve the required tolerances in semiconductor devices. This process is also expensive because it uses a costly reactive ion etch to remove portions of the metal layer 44 and the barrier layer 42. This process is even further expensive because the resist 50 pools over the bond-pad 20 and is time consuming to remove.
FIG. 2 is a cross-sectional view illustrating a portion of another embodiment of a microelectronic die 100 having a cap to protect a copper bond-pad. The die 100 illustrated in FIG. 2 is similar to the die 10 illustrated in FIG. 1, and thus like reference numbers refer to like components in both of these figures. The die 100 illustrated in FIG. 2 includes a cap 140 plated onto the bond-pad 20. The cap 140 is fabricated by constructing the first mask and forming a hole through the first and second dielectric layers 32 and 34 over the bond-pad 20. After forming the hole over the bond-pad 20, the cap 140 is plated onto the bond-pad 20 using a series of different plating cycles. For example, a palladium layer 142 can be plated directly onto the bond-pad 20 using a plating process. The palladium layer 142 provides a seed layer or nucleation layer for plating a nickel layer 144 onto the palladium layer 142 using another plating process. In some embodiments, a silver layer 146 can be plated onto the palladium layer 142 before depositing the nickel layer 144, and/or a gold layer 148 can be deposited onto the nickel layer 144.
One problem with the cap 140 illustrated in FIG. 2 is that the nickel initially plates onto one of the underlying metal layers and then continues to plate upon itself. The nickel, however, does not bond to the sidewalls of the opening through the dielectric layers such that oxygen and moisture can migrate along the interface between the nickel and the dielectric layers 32, 34 and 36. Therefore, the contact 140 does not sufficiently protect the copper bond-pad 20 from oxidation and corrosion.